global and scalable architecture the stb/pvr controller ic from teralogic is a key element of its global and scalable architecture for digital tv. it interfaces seamlessly to teralogic ? s digital tv decoder ics to create a versatile solution to design consumer electronics products such as digital set-top boxes, digital tv sets and personal video recorders (pvr) for cable, satellite or terrestrial broadcast. the se functions are integrated in a single ic ? multiple transport demux, descramblers, conditional access, pci bridge, cpu local bus, i 2 c, smartcard interfaces, ide interface, uart and gpios. this system-on-a-chip approach provides a very cost-effective solution by eliminating either the need to use discrete solutions or costly asic development. this ic address es worldwide digital tv requirements by incorporating four transport streams i/os and multiple demultiplexers that are compatible with atsc, arib, dvb, and directv . the universal appeal of this device is enhanced by the inclusion of dvb, directv des-ecb, mpeg des, triple des-cbc and multi-2 descrambling schemes. the controller ic can be used to design next generation pvr devices with advanced features or to upgrade an existing set-top box to include pvr functions. the multiple transport inputs enable consumer-pleasing capabilities such as the ability to simultaneously watch and record or to have digital picture-in-picture on any television set. multiple-transport, multiple-descrambler controller ic for consumer electronic oems to manufacture digital tv sets, digital set top boxes and personal video recorders TL811 stb/pvr controller ic cpu sdram
(unified for cpu) pci bus memory
controller
local bus
controller
pci bus transport in & out local bus transport in transport in descrambler 2
descrambler 1 t/s in 3 t/s in 2 t/s in 1 demux
1
demux
2
pvr i/o
ide
dtv i/o
i2c
smartcards
gpio
uart ide i2c smartcard gpio uart transport out t/s out atsc/dvb/directv /arib cpu interface
(sysad bus)
tl81x block diagram integrated circuits
copyright 2000. teralogic, inc. all rights reserved worldwide. teralogic and the teralogic logo are registered trademarks of te ralogic, inc. janus is a trademark of teralogic, inc. all other trademarks are properties of their respective owners and are acknowledged. 1 1/00 - 5k teralogic, inc. 1240 villa street mountain view ca 94041 tel 650.526.2000 fax 650.526.2006 www.teralogic.tv integrated circuits applications set-top boxes digital tv personal video recorders supporting teralogic products tl85x decoder ics cougar development platform programmable transport input/demultiplexer two dedicated and one bi-directional transport input ports one dedicated and one bi-directional transport output ports glueless interface to ieee 1394 devices two atsc/dvb/arib/directv compliant demux glueless interface to most front-end ics maximum input bit rate of 80 mbits/sec supported on each port ability to transfer multiple sd streams to the teralogic dtv decoder for sd pip applications ide ultra dma interface supports one ide connector for up to 2 ide drives ultra dma specifications allows 66 mbyte transfer rate sdram interface 32-bit wide sdram interface supports 16/64/128-mbit sdram devices pci bus interface 32-bit pci 2.1 compliant interface 50 mhz or 33 mhz bus clock pci master/slave/arbiter capability supported supports burst transfers for efficient data movement peripherals two iso-7816 smart card interfaces four asynchronous uart two i 2 c compatible master and slave ports three 32-bit timers/counters nrss-a/nrss-b support user-configurable general purpose i/os technology see grid below for packaging 2.5 v core, 3.3 v 1/0, 0.25 cmos 352 ball bga descramblers dvb, directv des-ecb, mpeg des, triple des-cbc, multi-2 descrambling supported simultaneous descrambling of two streams supported all three transport input ports can access the descramblers bypass mode of transport streams supported cpu interface glueless interface to mips cpus such as qed rm5231, nec v r 5432 32-bit wide multiplexed address/data supported write and read posting buffers between cpu and external resources (pci, memory bus and local bus). local bus generic bus interface (16-bit data and 24-bit address bus) 6 pre-decoded, programmable chip selects can be configured to be fixed 8-bit only, or 8- and 16-bit width device support TL811 stb/pvr controller ic pci bus teralogic
dtv decoder hd video transport out other devices if required analog hd out audio 5.1 out sd video out sd video capture flash eprom other i/o
required cpu sdram
pci bus memory
controller
local bus
controller
transport in & o ut local b us transport in transport in descrambler 2
descrambler 1
t/s in 3 t/s in 2 t/s in 1
dem ux
1
dem ux
2
pvr i/o
id e
dtv i/o
i 2 c
smartcards
gpio
uart ide i 2 c 2 smartcards gpio uart t/s out pod dtv tuner dtv tuner 1394 /dvcr TL811 tl85x cpu interface
(sysad bus)
TL811 system diagram
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